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PD - 91846B
SMPS MOSFET
Applications l Switch Mode Power Supply (SMPS) l Uninterruptable Power Supply l Power Factor Correction Benefits l Low Gate Charge Qg results in Simple Drive Requirement l Improved Gate, Avalanche and dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche Voltage and Current
IRFR1N60A IRFU1N60A
HEXFET(R) Power MOSFET
VDSS
600V
Rds(on) max
7.0
ID
1.4A
D-Pak IRFR1N60A
I-Pak IRFU1N60A
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
1.4 0.89 5.6 36 0.28 30 3.8 -55 to + 150 300 (1.6mm from case )
Units
A W W/C V V/ns C
Applicable Off Line SMPS Topologies:
l
Low Power Single Transistor Flyback
Notes
through
are on page 9
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1
3/7/03
IRFR/U1N60A
Static @ TJ = 25C (unless otherwise specified)
V(BR)DSS RDS(on) VGS(th) IDSS IGSS Parameter Drain-to-Source Breakdown Voltage Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. 600 --- 2.0 --- --- --- --- Typ. --- --- --- --- --- --- --- Max. Units Conditions --- V VGS = 0V, ID = 250A 7.0 VGS = 10V, ID = 0.84A 4.0 V VDS = VGS, ID = 250A 25 VDS = 600V, VGS = 0V A 250 VDS = 480V, VGS = 0V, TJ = 150C 100 VGS = 30V nA -100 VGS = -30V
Dynamic @ TJ = 25C (unless otherwise specified)
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 0.88 --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- --- --- --- 9.8 14 18 20 229 32.6 2.4 320 11.5 130 Max. Units Conditions --- S VDS = 50V, ID = 0.84A 14 ID = 1.4A 2.7 nC VDS = 400V 8.1 VGS = 10V, See Fig. 6 and 13 --- VDD = 250V --- ID = 1.4A ns --- RG = 2.15 --- RD = 178,See Fig. 10 --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz, See Fig. 5 --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 480V, = 1.0MHz --- VGS = 0V, VDS = 0V to 480V
Avalanche Characteristics
Parameter
EAS IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Typ.
--- --- ---
Max.
93 1.4 3.6
Units
mJ A mJ
Thermal Resistance
Parameter
RJC RJA RJA Junction-to-Case Junction-to-Ambient (PCB mount) Junction-to-Ambient
Typ.
--- --- ---
Max.
3.5 50 110
Units
C/W
Diode Characteristics
IS
ISM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- 1.4 showing the A G integral reverse 5.6 --- --- S p-n junction diode. --- --- 1.6 V TJ = 25C, IS = 1.4A, VGS = 0V --- 290 440 ns TJ = 25C, IF = 1.4A --- 510 760 nC di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFR/U1N60A
10
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
10
I D , Drain-to-Source Current (A)
1
I D , Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1
0.1
4.5V
4.5V
0.01 0.1
20s PULSE WIDTH TJ = 25 C
1 10 100
0.1 1 10
20s PULSE WIDTH TJ = 150 C
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
10
3.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 1.4A
I D , Drain-to-Source Current (A)
2.5
TJ = 150 C
2.0
1
1.5
TJ = 25 C
1.0
0.5
0.1 4.0
V DS = 100V 20s PULSE WIDTH 5.0 6.0 7.0 8.0 9.0
0.0 -60 -40 -20
VGS = 10V
0 20 40 60 80 100 120 140 160
VGS , Gate-to-Source Voltage (V)
TJ , Junction Temperature( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRFR/U1N60A
10000
VGS , Gate-to-Source Voltage (V)
V GS = 0V, f = 1MHz C iss = C gs + C gd, C dsSHORTED C rss = C gd C oss = C ds + C gd
20
ID = 1.4A VDS = 480V VDS = 300V VDS = 120V
16
C, Capacitance (pF)
1000
Ciss
100
12
8
C oss
10
4
Crss
1 1 10 100 1000
A
0 0 2 4 6
FOR TEST CIRCUIT SEE FIGURE 13
8 10 12 14
V DS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
10
100
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED BY RDS(on)
ID , Drain Current (A)
TJ = 150 C
1
10 10us
100us 1 1ms
TJ = 25 C
0.1 0.4
V GS = 0 V
0.6 0.8 1.0 1.2
0.1
TC = 25 C TJ = 150 C Single Pulse
10 100
10ms 1000 10000
VSD ,Source-to-Drain Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFR/U1N60A
1.6
VDS VGS
RD
ID , Drain Current (A)
1.2
RG 10V
D.U.T.
+
-VDD
0.8
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
0.4
VDS 90%
0.0 25 50 75 100 125 150
TC , Case Temperature ( C)
10% VGS
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
D = 0.50 1 0.20 0.10 0.05 0.02 0.01 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak TJ = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1
0.1
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U1N60A
EAS , Single Pulse Avalanche Energy (mJ)
15V
200
VDS
L
DRIVER
160
ID 0.65A 0.9A BOTTOM 1.4A TOP
RG
20V
D.U.T
IAS tp
+ V - DD
120
A
0.01
80
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
40
0 25 50 75 100 125 150
Starting T , Junction Temperature( C) J
I AS
Fig 12b. Unclamped Inductive Waveforms
QG
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
10 V
QGS VG QGD
V DSav , Avalanche Voltage (V)
770
750
Charge
730
Fig 13a. Basic Gate Charge Waveform
Current Regulator Same Type as D.U.T.
710
50K 12V .2F .3F
690
D.U.T. VGS
3mA
+ V - DS
670 0.0
A
0.4 0.8 1.2 1.6
I av , Avalanche Current (A)
IG ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
Fig 12d. Typical Drain-to-Source Voltage Vs. Avalanche Current
6
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IRFR/U1N60A
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS
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7
IRFR/U1N60A
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 1.27 (.050) 0.88 (.035)
2.38 (.094) 2.19 (.086)
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 1 2 3 0.51 (.020) MIN. 10.42 (.410) 9.40 (.370)
LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
-B1.52 (.060) 1.15 (.045) 3X 1.14 (.045) 2X 0.76 (.030) 2.28 (.090) 4.57 (.180) 0.89 (.035) 0.64 (.025) 0.25 (.010) M AMB
0.58 (.023) 0.46 (.018)
NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 9U1P INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE
Notes : T his part marking information applies to devices produced before 02/26/2001
IRFU120 9U 016 1P
DAT E CODE YEAR = 0 WEEK = 16
Notes : T his part marking information applies to devices produced after 02/26/2001
EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 1234 AS S EMBLED ON WW 16, 1999 IN T HE AS S EMBLY LINE "A" PART NUMBER
IRFU120 12 916A 34
INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE
DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A
8
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IRFR/U1N60A
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265) 6.35 (.250) -A5.46 (.215) 5.21 (.205) 4 6.45 (.245) 5.68 (.224) 1.52 (.060) 1.15 (.045) 1 -B2.28 (.090) 1.91 (.075) 9.65 (.380) 8.89 (.350) 2 3 6.22 (.245) 5.97 (.235) 1.27 (.050) 0.88 (.035) 2.38 (.094) 2.19 (.086) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006).
3X
1.14 (.045) 0.76 (.030)
3X
0.89 (.035) 0.64 (.025) M AMB
1.14 (.045) 0.89 (.035) 0.58 (.023) 0.46 (.018)
2.28 (.090) 2X
0.25 (.010)
I-Pak (TO-251AA) Part Marking Information
Notes : T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 9U1P INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE DAT E CODE YEAR = 0 WEEK = 16
IRFU120 016 9U 1P
Notes : T his part marking information applies to devices produced after 02/26/2001
EXAMPLE: T HIS IS AN IRFR120 WIT H AS S EMBLY LOT CODE 5678 AS S EMBLED ON WW 19, 1999 IN T HE AS S EMBLY LINE "A" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFU120 919A 56 78
DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A
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9
IRFR/U1N60A
Tape & Reel Information
TO-252AA
TR TRR TRL 16.3 ( .641 ) 15.7 ( .619 ) 16.3 ( .641 ) 15.7 ( .619 )
12.1 ( .476 ) 11.9 ( .469 )
FEED DIRECTION
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width 300s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Starting TJ = 25C, L = 95mH
RG = 25, IAS = 1.4A. (See Figure 12)
ISD 1.4A, di/dt 180A/s, VDD V(BR)DSS,
TJ 150C
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.3/03
10
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